Device improvements obtained from exploiting the dependence of physical characteristics of silicon at low temperature are above and beyond those improvements obtained from the usual geometric scaling of device dimensions. As device geometries continue to shrink into the deep submicrometer regime, second order effects begin to limit scaling alone further increases in device speed from scaling alone. Temperature scaling provides an additional variable for system optimization. The gain in performance at cryogenic temperatures, however isat the expense of inconvenience and additional cost for system refrigeration and of increased susceptibility to hot carrier degradation. Optimizing CMOS technology and design for low temperature applications can increase performance and reduce power dissipation without increasing hot carrier degradation.
