Design of DES encryption algorithm as bundleddata asynchronous pipeline using FPGA

Autores

  • Diego Augusto Silva Departamento de Ciência e Tecnologia Aeroespacial - Instituto Tecnológico de Aeronáutica - Divisão de Engenharia Eletrônica – São José dos Campos (SP), Brazil.
  • Duarte Lopes Oliveira Departamento de Ciência e Tecnologia Aeroespacial - Instituto Tecnológico de Aeronáutica - Divisão de Engenharia Eletrônica – São José dos Campos (SP), Brazil.
  • Gracieth Cavalcanti Batista Departamento de Ciência e Tecnologia Aeroespacial - Instituto Tecnológico de Aeronáutica - Divisão de Engenharia Eletrônica – São José dos Campos (SP), Brazil.

DOI:

https://doi.org/10.17563/rbav.v39i3.1179

Palavras-chave:

asynchronous logic, control, SCAs, pipeline, data-path, SoC, DPA

Resumo

Currently, digital systems that are able to meet major security restrictions are increasingly being demanded, both in the military and in commercial areas. Data security can be achieved by cryptographic algorithms. An important encryption algorithm known as data encryption standard (DES) was implemented in field programmable gate array (FPGA) in different synchronous architectures. In this paper, we have proposed the implementation of the DES algorithm in FPGA, in the asynchronous pipeline style. Compared to the implementation in FPGA using two different project styles, the proposed asynchronous obtained the average increase of 14.9% in throughput and the average reduction of 66.3% in latency.

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Publicado

2020-12-28

Edição

v. 39 n. 3 (2020)

Seção

Artigos