We describe two semiconductor processing developments. One of them is a1,25 micron design rule CMOS process that is fully operational with good yild in a class 100clean room. The Method of contrast enhanced lithograpy(CEL) is used for atter definition. The techniques of planarization and gate sidewall spacers is described. A second semiconductor process that is under development is for producing field effect transistors in a matrix array using amorphous silicon deposited on glass in a plasma enhanced CVD system. There are 160,000 transistors in the present 10cmx10cm array. Each transisto controls the voltage of an indium tin oxide pixel (transparent and conducting). A color filter with red, green, and blue elements forms the second parallel plate, white the liquid crystal in between. Transmitted liquid through the liquid crystal and color filter is controlled by the amorphous silicon PETs.
